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PROJECT

[2023] MetaVRain: A Low-power and Real-time Neural Rendering Processor and 3D Style Transfer System

      Demo Video: [link] / News: [link] [link] [link] [link] [link] / Interview: [link] / Dataset: [link]

    - Related paper: A 133mW Real-time Hyper-realistic-3D-NeRF Processor with 1D-2D Hybrid-Neural-Engines for Metaverse on Mobile Devices (ISSCC 2023)

    - Donghyeon Han's Contribution

        1) The Leader of the Project

        2) Development of Bundle-Frame-Familiarity (BuFF) Architecture

        3) Development of Temporal Familiarity based NeRF Acceleration Architecture

        4) Architecture Simulator Design of 1D-2D Hybrid Neural Engine

        5) Digital Circuit Design of 1D-2D Hybrid Neural Engine

        6) Development of Centrifugal Sampling based Dynamic Neural Network Allocation Method

        7) Development of Periodic Polynomial Approximation for Sinusoidal Function Approximation
        8) Digital Circuit Design of Modulo-based Positional Encoding Unit

        9) Back-end Design

        10) MetaVRain Embedded Board Design

        11) MetaVRain Demonstration Sysmte Design

[2022] HNPU-V1 & HNPU-V2: Fixed-point based Mobile Deep Neural Network Training System [AICAS Best Demonstration & Best Paper]

      Demo Video: [link] / News: [link] [link] [link]

    - Related paper: HNPU-V1: HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching (JSSC 2021)

    - Related paper: HNPU-V2: A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation (AICAS 2022)

    - Donghyeon Han's Contribution

        1) The Leader of the Project

        2) Development of Layer-wise Adaptive Precision Scaling Algorithm & Related Hardware

        3) Design of Fixed-point Representation based Reconfigurable Accumulation Network

        4) Back-end Design

        5) HNPU Embedded Board Design

        6) HNPU Demonstration System Design

[2021] OmniDRL: Low-power Deep Reinforcement Learning (DRL) Processor for Mobile DRL Simulator

      Demo Video: [link] / News: [link] [link]

    - Related paper: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dual-mode Weight Compression and On-chip Sparse Weight Transposer (S. VLSI 2021)

    - Donghyeon Han's Contribution

        1) Pytorch based Fine-grained Bit-precision Simulator Software Design

        2) 28-nm Place-and-route (PnR) of the Chip

 

[2020] GANPU: Energy-efficient Generative Adversarial Network (GAN) Training Processor for Mobile User-adaptation System

      Demo Video: [link] / News: [link] [link]

    - Related paper: 7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation (ISSCC 2020)

    - Donghyeon Han's Contribution

        1) Exponent based Output Prediction Algorithm Development

        2) Low-area & Low-power Output Prediction IP Design

        3) Design of Pipeline Structure between Main Convolution Core and Output Prediction IP

[2019] DF-LNPU: World's 1st Real-time Online Deep Neural Network Training Processor for Object Tracking in Mobile Devices

      News: [link] [link] / Patent: [link]

    - Related paper:

        1) A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture (S. VLSI 2019)

        2) DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning (JSSC 2021)

    - Donghyeon Han's Contribution

        1) The Leader of the Project

        2) Development of New DNN Training Algorithm: Pipelined Direct Feedback Alignment (PDFA)

        3) Front-end Design (Verilog) of PDFA based Heterogeneous DNN Training Cores

        4) Back-end Design (PnR) of DF-LNPU

[2019] LNPU: World's 1st Deep Neural Network On-device Training Processor for Mobile Devices [ISSCC Best Demonstration]

      Demo Video: [link] / News: [link]

    - Related paper: LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16 (ISSCC 2019)

    - Donghyeon Han's Contribution

        1) 65-nm Place-and-route (PnR) of the Chip

        2) Front-end Design (Verilog) of Batch-normalization Unit (IncludingBack-propagation Functionality)

[2018] Mobile 3D Hand Gesture Recognition (HGR) System with CNN-stereo based Depth-estimation and ICP-PSO based Hand Tracking [ISSCC Best Demonstration]

      Demo Video: [link]

    - Related paper: A 9.02mW CNN-Stereo based Real-time 3D Hand Gesture Recognition Processor for Smart Mobile Devices (ISSCC 2018)

    - Donghyeon Han's Contribution

        1) 3D Hand Model Extraction

        2) ICP-PSO based Hand Tracking Algorithm Development

        3) 3D Hand Sphere Model Design (UI)

[2017] K-eye Ultra-low-power Mobile Face Recognition System

      Demo Video: [link] [link] / News: [link]

    - Related paper: A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector (JSSC 2017)

    - Donghyeon Han's Contribution

        1) Haar-like based Face Detection FPGA IP Development

        2) Bluetooth FPGA IP Development for Wireless Face Detection Result Transmission

        3) C# based Face Recognition UI Development

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